Analog Fault Simulation: Key to Product Quality, or a Foot in the Door

Although much has changed in the last few years, mixed-signal design communities have been lethargic to adopt digital Design for Test (DfT), fault simulation, and defect-oriented testing for digital blocks within mixed-signal devices. This inertia is far more evident for complex, mixedsignal devices that resist divide and conquer techniques. Use of digital scan insertion, fault simulation, fault grading and subsequent Automated Test Pattern Generation (ATPG) is not simply a matter of the design team adopting new EDA tools. To effectively use the former, physical alteration of the design is required to provide access to critical nodes at primary inputs and outputs of the Device Under Test (DUT). Can it be hypothesized that mixed-signal SOC designs will require an equal or greater amount of design alteration? Now consider blocks that are “channel integrity sensitive” such as cellular phone-voiceband codecs and hard disk drive read channels. These blocks tend to follow Heisemberg’s “relation of uncertainty”, which expresses the issues of interaction and interference existing between any process of observation and the objects observed. Further embed those channels deep into the hierarchy of a design, and this is the stuff that may defy analog fault simulations.